1. Field of Invention
The invention relates to a data packet processing device and the method thereof. In particular, the invention relates to a device and a method that use a hardware based TCP/IP traffic offload engine (TOE) device to improve the input/output traffic load between network nodes.
2. Related Art
With the rapid development of networks, the most commonly seen communication speed between network nodes has increased from 10 Mbps/100 Mbps in early days to 1 Gbps nowadays. One naturally expects that it will go up to 10 Gbps in the near future. However, as the transmission speed between network nodes increases continuously, the processing speed at the nodes do not have an increase in proportion. Therefore, each network node has to upgrade its hardware equipment or increase the number of hardware devices (through a multiple processor system or a clustered system) in order to satisfy the speed requirement.
The very reason for the above-mentioned problem is actually the cornerstone toward the popularization of the network, namely, the TCP/IP protocol. TCP/IP is the primary protocol in current network systems. Traditionally, one uses software to process packet input/output (IO) load according to the TCP/IP protocol installed in the operating system (OS) kernel. However, in order to provide a flexible module design and to achieve reliability transmissions, the TCP/IP protocol contains a very complicated stack design. Therefore, a lot of computing resources have to be spent on processing network packet 10 in order to executing an additional huge and highly complicated protocol stacking procedure. The result is that the whole network packet processing efficiency is extremely low. Therefore, the network node processing mechanism implemented by software cannot satisfy the increasing network transmission speed.
Among the disclosed prior art, the U.S. Patent Application Nos. 20020107971 and 20020087732, and the U.S. Pat. No. 6,591,302 all use an additional processor along with built-in routines to provide traffic offload. In particular, the U.S. Patent Application Nos. 20020107971 discloses a processor mechanism that processes individual transmission requests and receives packets. The U.S. Patent Application Nos. 20020087732 and the U.S. Pat. No. 6,591,302 further describe the implementation of two additional processors and a peripheral auxiliary circuit design. Although such solutions have the advantage of being more flexible so that it can be rapidly developed and mended if there is any problem, it costs a lot in the implementation and the transmission latency is longer. Therefore, it is not suitable for such applications as terminal interfaces and real-time audio/video presentations.
On the other hand, the U.S. Pat. No. 6,483,840 addresses the problem of how to use a full hardware structure to solve the traffic offload problem. This patent is based upon the OSI network structure. It uses two built-in hardware processing units to process the Layer 3 and Layer 4, achieving the goal of helping with traffic offloads. In comparison with the hardware-along-with-software solution, this structure has a better performance in processing latency. Nonetheless, it is still based upon the most primitive OSI network structure. It keeps the stacking concept in the hardware module design. Thus, the traffic offload solution cannot be optimized.
Consequently, it is imperative to provide a solution that can simultaneously process the traffic offload and solve the transmission latency problem. It does not only break the limitation of existing network structures, but really achieves efficiency optimization.